Silicon-Based Passive and System-in-Package Integration: Options for Atomic Layer Deposition

By: Dr. Fred Roozeboom, Dr. Erwin Kessels, Material Matters Volume 1 Article 3

Dr. Fred Roozeboom, NXP Semiconductors Research and
Dr. Erwin Kessels, University of Technology, Eindhoventd

In the past decade, the integration of passive components in silicon and the further 3D integration and stacking of individual chips from different technologies (e.g. CMOS, GaAs, MEMS) into one package (‘heterogeneous’ integration) have been developed to such an extent that now the first mass-volume production has begun. Today, the International Technology Roadmap for Semiconductors includes the future projections for the next generation Si-based Integrated Passives and System-in-Package integration.1

Recently, the first highly-integrated cellular RF transceiver systems based on the use of these technologies were launched.2 Here, amongst others, Philips (now NXP) Semiconductors, utilizes back-end silicon processing to integrate passive components onto a silicon substrate that can act as a carrier for the heterogeneous integration of active component dies, MEMS dies, etc.3 As an example, a transceiver IC can be flip-chip mounted onto this passive component silicon substrate, thus minimizing interconnect parasitics and the footprint area. This sub-assembly is then flipped back into a standard leadframe package (Figure 1).3


Figure 1. Passive die with active transceiver die flipped on top, doubleflipped on a lead frame (left open, without moulding compound). This is an example of a Bluetooth System-in-Package ‘plug and play’ radio module. (From Ref. 3).

The passive die is made in the so-called PICS (Passive Integration Connecting Substrate) technology developed to integrate passive components such as high-Q inductors, resistors, accurate MIM capacitors and, in particular, highdensity (~30 nF/mm2) MOS ‘trench’ capacitors for decoupling and filtering. These are fabricated in silicon by dry-etching arrays of macropores with ~1.5 μm width and up to ~30 μm depth. Trench capacitors filled with ~ 30 nm silicon oxide and nitride (‘ONO’) dielectrics and a poly-Si/ Al top electrode showed superior dielectric breakdown voltage (30 V typical), very low leakage current, and long lifetime.4,5

A next miniaturization step includes the use of so-called highk dielectrics (based on HfO2, etc.) to compose MIS and MIM trench capacitors with increased capacitance densities of ≥200 nF/mm2. One step towards System-in-Package is the etching and Cu-filling (electroplating) of viaholes of 10–200 μm widths and depths up to 300 μm. Vias are through-wafer holes filled with materials for heat spreading, electrical grounding and low-inductance signal interconnection from one wafer side to the other. This concept makes way for 3D die-stacking and generic System-in-Package integration with small form factor.

One of the major challenges in realizing high-density trench capacitors and in making through-wafer vias for 3D wafer and die stacking is to find an attractive pore lining and filling fabrication technology at reasonable cost and reaction rate as well as low temperature (for back-end processing freedom). The deposition for the insulating, dielectric, and performed at conductive layers (i.e. electrodes, seed layers and Cu-diffusion barriers) should be highly uniform and step-conformal and low-temperature (≤400 °C). Atomic Layer Deposition (ALD) is an enabling candidate here, by virtue of the self-limiting mechanism of this layer-by-layer deposition technique. A substrate surface is submitted to alternating exposures to vapors of two reagents, for example, trimethylaluminum (TMA) and water vapor in the case of Al2O3 deposition. Through its self-limiting surface reactions, ALD enables the uniform lining or filling of high aspect ratio pores with (sub)monolayer control. The self-limiting character provides inherent conformality, as demonstrated for even challenging devices like deep DRAM trench capacitors with ~60:1 aspect ratios at design rules below 100 nm.6 Yet, ALD process improves the production of many other devices with a large topology, such as viaholes in stacked dies, MEMS, planar waveguides, multilayer optical filters, and layers protecting against diffusion, oxidation, corrosion, etc.

The application of ALD in trench capacitors and viaholes leads to additional challenges relative to flat wafers. For example, for the ALD of oxides the roughness on the trench sidewalls may cause undesired lower breakdown voltages. Also, the formation of interfacial oxide layers may lead to undesired low relative dielectric constants (cf. Figure 2). A proper precleaning procedure (e.g. HF dipping, rinsing) is essential to minimize this. Furthermore, a proper uniform layer thickness and microstructure (morphology and texture) over the entire pore depth is necessary to achieve good insulating layers, and are certainly not obvious. Adsorption and desorption play an important role in filling and emptying the pores. In particular, at the given pressure and macropore dimensions the ALD process proceeds in a different diffusion regime (Knudsen diffusion) limiting the free diffusion of the gaseous ALD reagents and products. Timing of the cycling of the gases, including extended purging steps, needs to be optimized for additional adsorption and desorption processes of precursors.7 Only then ideal nanolaminates can be achieved.

For the deposition of conductive layers by ALD, for the application as electrodes, seed layers, diffusion barriers (e.g. against Cu-diffusion in vias) there is a substantial choice between thermal and plasma-assisted ALD. The plasmabased process can lead to improved material properties as has clearly been demonstrated by results on conductive TiN films.8 The process based on TiCl4 dosing in combination with H2-N2 plasma exposure has yielded thin TiN films with excellent resistivity and low impurity levels (C, H, Cl, etc.) greatly surpassing the material quality achieved with the thermal process employing NH3 dosing. Moreover, in terms of acceptable material quality, the thermal process is limited to the substrate temperature range of 300–400 °C while the plasma-based process can yield fair material properties down to temperatures as low as 100 °C.


Figure 2. (a) SEM cross-section and (b) high-resolution TEM image of an Al2O3/HfO2/Al2O3 dielectric layer stack, grown by thermal ALD with a poly-Si electrode layer on top.

TiN films deposited by plasma-assisted ALD for application as electrode materials in trench capacitors have already been explored (Figure 3). Another benefit from the plasma process is that tailoring the plasma composition and exposure time as shown for metal nitrides such as TiN and TaN can control the stoichiometry of the films. For example, for TaN deposited from metalorganic precursors (e.g., pentakisdimethyl aminotantalum) it is possible to tune the properties from insulating N-rich TaN by using a H2-N2 plasma, to low-resistivity TaN by using a relatively long H2 plasma exposure, to very low resisitivity TaCN films with a large amount of carbon using a relatively short H2 plasma exposure.


Figure 3. (a) SEM cross-section and (b) high-resolution TEM image of a MOS stack consisting of 30 nm ‘ONO’ dielectric and 10 nm plasma-assisted ALD TiN with 0.3 μm LPCVD grown poly-Si on top.

ALD is, in principle, ideal for depositing nanolaminate stacks, for example oxide/nitride multilayers used in trench capacitors. Multilayer stacks of ‘high-k’ dielectric layers (Al2O3, Ta2O5, HfO2, etc.) and conductive layers (TiN, TaN) on wafers with a large topography enable MIM capacitors with ultrahigh capacitance density. A challenging example is given in Figure 4. The TEM images show the potential of ALD in growing multilayer stacks in high aspect ratio features. In our macropore arrays described above, a multilayer stack of 20 nm Al2O3 // 25 nm TiN // 20 nm Al2O3 // 25 nm TiN was deposited in 35 μm deep pores from TiCl4 and NH3 using thermal ALD. Here, the Al2O3 was grown from trimethylaluminum and O3 plasma at 380 °C and the TiN was grown from TiCl4 and NH3 at 400 °C. It appeared that the layer thickness all along the pores was, within 10 % accuracy, 20 nm for the Al2O3 and 25 nm for TiN.

Figure 4. TEM images of a 20 nm Al2O3 // 25 nm TiN // 20 nm Al2O3 // 25 nm TiN multilayer grown in a pore with ~35 μm depth; a) overview image displaying both sides of one pore (top); b) and c) images at the upper part of the pore; d) image at ~25 μm pore depth. ALD performed by H.D. Kim, Jusung Engineering.

It can be concluded that the manufacturing of ultrahigh density (>200 nF/mm2) capacitors is within reach and the same holds for growing seed layers for Cu-electroplating in viaholes and Cu-diffusion layers such as TaN. Thus there is a bright prospect for ALD in passive and heterogeneous integration, provided ALD is further developed to maturity and cost factors are reduced (e.g. development of batch ALD to compensate for low growth rates in single-wafer ALD). Also the development of low-temperature processing is important. This will be further facilitated by the availability of novel and dedicated precursor chemicals.

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Acknowledgement

The technical contributions by J. Klootwijk, W. Dekkers and M. Kaiser (Philips) and S. Heil (TU Eindhoven) are gratefully acknowledged.

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References

  1. ITRS Roadmap 2005 edition, Assembly and Packaging, see: www.itrs.net/Links/2005ITRS/Home2005.htm.
  2. www.3d-ic.org/literature.html.
  3. F. Roozeboom, A.L.A.M. Kemmeren, J.F.C. Verhoeven, F.C. van den Heuvel, J. Klootwijk, H. Kretschman, T. Frič, E.C.E. van Grunsven, S. Bardy, C. Bunel, D. Chevrie, F. LeCornec, S. Ledain, F. Murray and P. Philippe, Thin Solid Films 2006, 504, 391.
  4. F.Roozeboom, A.Kemmeren, J.Verhoeven, F.van den Heuvel, H.Kretschman and T.Frič, Mat. Res. Soc. Symp. Proc. 2003, 783, 157.
  5. F. Roozeboom, A.L.A.M. Kemmeren, J.F.C. Verhoeven, F.C. van den Heuvel, J. Klootwijk, H. Kretschman, T. Frič, E.C.E. van Grunsven, S. Bardy, C. Bunel, D. Chevrie, F. LeCornec, S. Ledain, F. Murray and P. Philippe, Electrochem. Soc. Symp. Proc. 2005, 2005,16.
  6. M. Gutsche, H. Seidl, J. Luetzen, A. Birner, T. Hecht, S. Jakschik, M. Kerber, M. Leonhardt, P.Moll, T.Pompl, H.Reisinger, S. Rongen, A. Saenger, U. Schroeder, B. Sell, A. Wahl and D. Schumann, Tech. Digest IEDM 2001, 18.6
  7. J. Klootwijk, A. Kemmeren, R. Wolters, F. Roozeboom, J. Verhoeven, E. van den Heuvel, in ‘Defects in Advanced High-κ Dielectric Nano-Electronic Semiconductor Devices’, (E. Gusev, ed.); Springer: Dordrecht, 2006, p. 17.
  8. S.B.S. Heil, E. Langereis, F. Roozeboom, M.C.M. van de Sanden and W.M.M. Kessels, J. Electrochem. Soc. 2006, 153, G956-G965.

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