Bottom-gate bottom-contact field-effect transistors (FETs) were fabricated in a nitrogen atmosphere on highly doped Si-wafers with a thermally grown 250 nm SiO2 layer. The two layers served as the gate electrode and gate insulator. Au source and drain electrodes (30 nm thick) were defined by standard photolithography:
channel length (L) = 10 mm
channel width (W) = 10 mm
A homogeneous solution of PTAA was prepared in toluene at room temperature containing 1.0 wt% of the polymer. This solution was deposited via spin-coating at 500 rpm for 30 seconds followed by 2,000 rpm for 50 seconds.
Electrical characterization of the PTAA FETs was conducted in a nitrogen atmosphere with a HP4155B semiconductor parameter analyzer. Field-effect mobilities were calculated from transfer characteristics (saturation regime) employing the relation:3
Isd is the source-drain current (saturation regime)
Vg and Vsd gate and soxce-drain voltage, respectively
Ci the insulator capacitance
W and L the channel width and length
V0 the turn-on voltage
Transfer and output curves for PTAA transistors are shown in Figures 1 and 2.
Figure 1.Transfer output curves for PTAA transistors corresponding to field effect mobility of 4 x 10–3 cm2/Vs.
Figure 2.Output curves for PTAA transistors corresponding to field effect mobility of 4 x 10–3 cm2/Vs.
Data courtesy of Dr. Iain McCulloch, Imperial College London and Flexink, Inc.